1. Field of the Invention
The present invention relates to a shift register; in particular, to a shift register for reducing the number of clock control signals thereof, and a driving circuit and a display device using the same.
2. Description of Related Art
Nowadays the thin-film transistor (TFT) made from amorphous silicon (a-Si:H) is used in most liquid crystal displays (LCD). In the design of the large LCD panel, a driving integrated circuit is designed to surround the LCD panel. The gate voltage of the TFT is used for controlling the TFT to be on or off, wherein the corresponding pixel is driven by the source of a driving signal at proper timing through the on/off state of the TFT. As a result, each of the display pixels can function independently without being influenced by other display pixels.
The driving circuits in an LCD, like a scan driving circuit and a data driving circuit, are mainly coordinated with a clock control signal to output in order the scan driving signal and the data driving signal to the next stage shift register within a fixed duty cycle so as to drive each of the scan lines and the data lines in the LCD panel.
FIG. 1A is a circuit diagram of a shift register employed by a conventional N-type metal-oxide-semiconductor field-effect transistor (MOSFET). FIG. 1B is a timing diagram of the circuit operation of FIG. 1A. Referring to FIGS. 1A and 1B, within the period of T1, when an input signal Gn−1 is a logic-high voltage, transistors N1 and N7-N8 are turned on such that the voltage of a node “P2” is pulled down to a logic-low voltage, that is, transistors N5-N6 and N10 are turned off. Meanwhile, a clock signal CLK1 inputs a logic-high voltage from a node “c1” such that a transistor N2 is turned on and the voltage of a node “P1” is pulled up to conduct a transistor N9. Next, within the period of T2, a clock signal CLK2 inputs a logic-high voltage from a node “c2” to change an output signal Gn into a logic-high voltage and transmit the logic-high voltage to the next stage device.
Within the period of T3, the input signal Gn−1 is a logic-low voltage and the transistors N1 and N7-N8 are turned off. Meanwhile, the clock signal CLK1 inputs a logic-low voltage from the node “c1” so that the transistor N2 is turned off. The voltage of the node “P1” is sufficient to turn on the transistor N9. The output signal Gn changes into a logic-low voltage because of the logic-low voltage inputted from the node “c2” by the clock signal CLK2 and is transmitted to the next stage device. Within the period of T4, a clock signal CLK3 inputs a logic-high voltage from a node “c3” to turn on transistors N3-N4. The voltage of the node “P2” is pulled up to turn on the transistors N5-N6 and N10, and the voltages of the node “P1” and the output signal Gn are pulled down to logic-low voltages such that the resetting operation of the shift register is completed.
The foregoing single shift register requires 3 sets of clock signals CLK1-CLK3 to complete operation within the periods of T1-T4. The circuit consisted of a plurality of shift registers requires at least 4 sets of clock signals CLK1-CLK4 for controlling. FIG. 2A is a circuit block diagram of a conventional scan driving circuit consisted of a plurality of shift registers of different stages. FIG. 2B is a timing diagram of the circuit operation of FIG. 2A. Referring to FIGS. 2A and 2B, a first stage shift register 201 receives a scan driving signal SP. The first shift register 201 utilizes clock signals CLK1, CLK2 and CLK3 to output a signal G1 during the period of T2 through the input nodes “c1”, “c2” and “c3” (the same as the circuit operation of a single shift register 100 of FIG. 1A).
A second stage shift register 202 receives the output signal G1 from the last stage shift register 201 and utilizes clock signals CLK2, CLK4 and CLK1 to output a signal G2 within the period of T3 through the clock input nodes “c1”, “c2” and “c3”. A third stage shift register 203 receives the output signal G2 from the last stage shift register 202 and utilizes clock signals CLK4, CLK3 and CLK2 to output a signal G3 within the period of T4 through the clock input nodes “c1”, “c2” and “c3”. A fourth stage shift register 204 receives the output signal G3 from the last stage shift register 203 and utilizes clock signals CLK3, CLK1 and CLK4 to output a signal G4 within the period of T5 through the clock input nodes “c1”, “c2” and “c3”.
In the prior art, a multiple-stage shift register requires 4 sets of clock control signals to output one type of signal and cannot generate other complementary output signals to drive other pixel circuits. For instance, the driving circuit of an LCD with an organic light emitting diode (OLED) has to be supplied with additional control signals in order to complete the operation of driving the OLED. Moreover, since a shift register operates by transmitting the output signal from the last stage shift register as its own input signal to the next stage shift register, if an output impedance of the shift register is too large, a mistake in the level of the output signal from the last stage shift register would occur because of the loading effect of the next stage shift register, and cause the circuit operation to function abnormally. Besides, the said situation also creates overlapping of the output signals from shift registers of different stages. If such shift registers that may cause output signal overlapping are used in the scan driving circuit, two scan lines may be opened during the same time period, and the frame display is therefore rendered abnormal.
Furthermore, for LCD panels of medium and small sizes, for instance, the display panels of the cellular phone and the personal digital assistant (PDA), the driving circuit is designed to be disposed on the glass substrate of the LCD panel. Hence, a thin-film transistor (TFT) made from low temperature polycrystalline silicon (LTPS) is required. However, the driving circuit disposed on the glass substrate of the LCD panel is probably to be limited by unsatisfactory characteristics of the transistor element, such as low mobility, shifting threshold voltage and large leakage current. Therefore, during designing the driving circuit on the LCD panel, the above problems have to be especially taken into consideration so as to select appropriate elements. Generally speaking, during the process of manufacturing low temperature polycrystalline silicon, the P-type metal-oxide-semiconductor field effect transistor (MOSFET) is one of the elements whose characteristics possess better reliability.